Power consumption of electronic devices that include integrated circuitry is increasingly becoming an important issue for any one or more of a number of reasons. For example, as the operating speeds of integrated circuits (ICs) continually increase, in general so, too, do the power requirements for these circuits, since power consumption varies in direct relation to the operating speed. In addition, as each new generation of technology brings a decrease in feature size and an increase in integration scale, power consumption of ICs generally increases due to the sheer presence of many more circuit elements, e.g., transistors and the like. Furthermore, with the increasing integration scale, electronic devices are capable of supporting more and more features. Power consumption typically increases with greater numbers of features, particularly when a feature requires circuitry that would not be needed in the absence of that feature. Moreover, with decreasing feature sizes comes an increasing amount of leakage current. For example, while fabrication technologies of only a short time ago resulted in leakage current on the order of only a few percent of total power, current fabrication technologies yield current leakage rates of 30% to 40% or more.
There are a number of methods for reducing power consumption of ICs. One method is to simply reduce the systemic operating voltage of the IC. While this method has the ability to significantly reduce the power consumption of ICs (e.g., reducing the operating voltage from 5V to 3.3V results in a gross power reduction of about 56%), there are practical limits to this method. Another method of reducing power consumption of ICs is to reduce the amount of logic circuitry. There are clearly practical limits to this method as well. Consequently, one, the other or both of these methods are typically used in connection with one or more power management methods that seek to reduce the power provided to portions, or “functional blocks,” of ICs during periods when these blocks are not needed.
One known power-management technique is to strategically place functional blocks onto voltage islands that can be separately powered up only when needed and down when needed. A challenge with this approach, especially when the functional blocks are relatively large and include many latches, is ensuring that the latches in a power-down functional block are in the state necessary when that functional block is powered back up. One way of handling this is to use a scan-chain method in which the states of all of the latches in a functional block to be powered down are scanned out to an off-voltage-island memory just prior to powering down. When the functional block is powered up again, the stored states are then scanned back into the latches just prior to use. A shortcoming of this approach is that there is a large overhead in the many clock cycles used up in the scanning-in and -out of the states. The greater the number of latches needed to be restored, the larger the overhead. Another way to handle the startup-state issue is to use state-saving latches for all of the latches having states that need to be restored when the functional block is re-powered-up. A drawback of this approach is that state-saving latches are much more complex than non-state-saving latches and, therefore, require much more chip real estate than non-state-saving latches.